Nowadays, many electrical appliances are widely used with computers due to the amazing power of computers. For example, video compact disks (VCDs) and digital versatile disks (DVDs) are able to be played by a personal computer. Since the size of a typical computer monitor is not large enough to exhibit the spectacular video effect of the VCD or DVD disks, it is preferred that the signals be outputted from the personal computer to a TV set to be displayed on the relatively large TV screen. The purpose can be achieved by employing a display adapter.
FIG. 1A is a partial functional block diagram of a typical display adapter. The pixel parallel digital signals from a graphic chip 10 are selectively converted into a proper format of analog signals via either a random access memory digital-to-analog converter (RAM DAC) 11 or a TV encoder 12, and delivered to a computer monitor 13 or a TV screen 14, respectively, for display. Further, for TV analog signals, two formats, i.e. the NTSC (National Television Standards Committee) standard and the PAL (Phase Alternate Line) standard, are involved.
The partial functional block diagram of the TV encoder 12 can be seen in FIG. 1B. The pixel parallel digital signals from the graphic chip 10 are processed by a data capture device 121, a color space converter 122, a scaler and deflicker 123, a first-in first-out buffer 124, an NTSC/PAL encoder 125 and a digital-to-analog converter 126 to produce the TV analog signals either in the NTSC or PAL standard.
The scaler and deflicker 123 is used for processing a non-interlacing scan data and then outputting the processed non-interlacing scan data to the first-in first-out buffer 124. The NTSC/PAL encoder 125 accesses the data from the first-in first-out buffer 124 to separate it into an odd field and an even field, resulting in that an interlacing scan data is displayed on the TV screen. The time for processing two horizontal scan lines by the scaler and deflicker 123 is equal to that for processing one horizontal scan line by the NTSC/PAL encoder 125. Thus, the relationship between the frequency Fsd of the clock signal required for the scaler and deflicker 123 and the frequency Fe of the clock signal required for the NTSC/PAL encoder 125 can be represented by the following equation (1):Fsd/Fe=2×H—sd/H—e  (1),wherein H_sd represents the number of pixels in a horizontal scan line processed by the scaler and deflicker 123, while H_e represents the number of pixels in a horizontal scan line processed by the NTSC/PAL TV encoder 125.
Conventionally, the TV encoder 12 uses a single phase-locked loop (PLL) clock signal generator 127 to generate a clock signal simultaneously provided to the scaler and deflicker 123 and the NTSC/PAL TV encoder 125. In other words, Fsd=Fe. When larger and larger pixel number, e.g. 1024 points, 1152 points, 1365 points or even 1600 points, for each horizontal scan line in the non-interlacing image data needs to be processed by the scaler and deflicker 123, the processed image width displayed on the TV frame becomes narrower than expected. It is because the frequency Fsd is increased with the pixel number in a scan line. In the case that Fe equals to Fsd, the frequency Fe increases accordingly. The increasing frequency Fe will speed up the output frequency of individual pixel in the scan line and thus shorten the distance between every two adjacent pixels on the TV screen. In other words, a seemingly compressed image is shown. Thus, the original width of the TV screen is not efficiently used.
Therefore, the purpose of the present invention is to develop a clock signal synthesizer with multiple frequency outputs and a method for synthesizing a clock signal for use with a TV encoder to deal with the above situations encountered in the prior art.